A semiconductor memory device may include an electrically floating body in which an electrical charge is stored. The electrical charge stored in the electrically floating body may represent a logic high or “1” data state or a logic low or “0” data state.
Various techniques may be employed to read data from and/or write data to a semiconductor memory device having an electrically floating body. In one conventional technique, a semiconductor memory device having a memory cell with a memory transistor may be read by applying a bias to a drain region of the memory transistor, as well as a bias to a gate of the memory transistor that is above a threshold voltage of the memory transistor. As such, this conventional reading technique may sense an amount of channel current provided/generated in response to the application of the bias to the gate of the memory transistor to determine a state of the memory cell. For example, an electrically floating body region of the memory cell may have two or more different current conditions/states corresponding to two or more different logical states (e.g., two different current conditions/states corresponding to two different logic states: a binary “0” data state and a binary “1” data state).
Also, conventional write techniques for semiconductor memory devices having memory cells with N-Channel type memory transistors typically result in an excess of majority charge carriers in electrically floating body regions of the memory transistors by channel impact ionization or by band-to-band tunneling (gate-induced drain leakage “GIDL”). The majority charge carriers may be removed via drain side hole removal, source side hole removal, or drain and source side hole removal by, for example, using back gate pulsing.
Often, conventional read and write techniques may utilize a large number of voltage drivers (for example, a voltage driver per source line (SL)) which may occupy a large amount of area on a circuit board or die. Also, pulsing between positive and negative gate biases during read and write operations may reduce a net quantity of charge carriers in a body region of a memory cell of a semiconductor memory device, which, in turn, may gradually eliminate data stored in the memory cell. In the event that a negative voltage is applied to a gate of a memory cell transistor, thereby causing a negative gate bias, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may recombine with majority charge carriers, which may be attracted to the gate, and net charge majority charge carriers located in the floating body region may decrease over time. This phenomenon may be characterized as charge pumping, which is a problem because the net quantity of charge carriers may be reduced in the memory cell, which, in turn, may gradually eliminate data stored in the memory cell.
In addition, conventional read and write techniques may utilize multiplexer circuitry to selectively apply one or more bit lines to the input of a sense amplifier. The multiplexer circuitry may add complexity and latency to read and/or write operations. Additionally, the multiplexer circuitry may introduce unwanted capacitance and inductance which may reduce margins of the read and/or write operations.
In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with conventional read and write techniques involving semiconductor memory devices.